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-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:44:29 11/23/2010 
-- Design Name: 
-- Module Name:    Conf_Buffer - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use WORK.CONSTANTS.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Conf_Buffer is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
			  sel : in STD_LOGIC;
           addr_and_we : in  STD_LOGIC_VECTOR(ADDR_SIZE_CONFBUFFER-1 downto 0);
           load : in  STD_LOGIC;
           data_in : in  STD_LOGIC_VECTOR(DATA_SIZE-1 downto 0);
           data_out : out  STD_LOGIC_VECTOR(DATA_SIZE-1 downto 0));
end Conf_Buffer;

architecture Behavioral of Conf_Buffer is

component One_hot_count3 is
    Port ( reset : in  STD_LOGIC;
           advance : in  STD_LOGIC;
			  clk : in STD_LOGIC;
           count_out : out  STD_LOGIC_VECTOR (ADDR_SIZE_RESBUFFER-2 downto 0) );
end component;

component REG32 is
	port (
		data_in		:	in std_logic_vector(DATA_SIZE-1 downto 0);
		data_out	:	out std_logic_vector(DATA_SIZE-1 downto 0);
		we			:	in std_logic;
		clk			:	in std_logic;
		reset		:	in std_logic
	);
end component;

signal outcount : std_logic_vector (ADDR_SIZE_CONFBUFFER-2 downto 0);
signal reg0out, reg1out, reg2out, reg3out : std_logic_vector(DATA_SIZE-1 downto 0);
signal tmp_data_out : std_logic_vector(DATA_SIZE-1 downto 0);

begin
-- purpose : Internal pointer used to select between the 3 configuration strings.
-- type    : behavioral
counter: One_hot_count3
	port map(reset, load, clk, outcount);

-- purpose : 3 Internal registers
-- type    : behavioral
reg0 : REG32
   port map(data_in, reg0out, addr_and_we(0), clk, reset);

reg1 : REG32
   port map(data_in, reg1out, addr_and_we(1), clk, reset);

reg2 : REG32
   port map(data_in, reg2out, addr_and_we(2), clk, reset);

reg3 : REG32
   port map(data_in, reg3out, addr_and_we(3), clk, reset);

-- purpose : configuration string selection
-- type    : behavioral
buffer_exit : process(outcount, reg0out, reg1out, reg2out, reg3out)
begin
case outcount is 
	when "001" =>
		tmp_data_out <= reg1out;
	when "010" =>
		tmp_data_out <= reg2out;
	when "100" => 
		tmp_data_out <= reg3out;
	when others =>
		tmp_data_out <= (others => '0');
end case;
end process;

-- purpose : output selection between the IJTAG configuration strings and the gateway configuration string.
-- type    : Sequential.
data_out <= tmp_data_out when sel ='0' else
				reg0out      when sel ='1' else
				(others => '0');
	

end Behavioral;

